Copending application, Ser. No. 233,107 now abandoned, filed Feb. 10, 1981 for Marc L. Harrison discloses the use of logic circuitry for processing data during unused clock time between master and slave latches. Copending application Ser. No. 233,143, now U.S. Pat. No. 4,399,516, filed for D. E. Blahut-M. L. Harrison-M. J. Killian-M. E. Thierbach on the same date as that application, discloses the use of logic circuitry between master and slave latches to permit the use of programmed logic arrays (PLA's) of reduced size in microprocessors to perform the function of relatively large prior art PLA's. The latter application also teaches the implementation of a hierarchical PLA control arrangement for microprocessors.
In the latter application, the gating of clock pulses applied to the input register of a PLA, particularly when under the control of another PLA, permitted a relatively enriched repertoire of actions to be orchestrated by a PLA of a given size. The application also disclosed the gating of data into an input register of a PLA under the control of a second PLA. Arrangements of the type disclosed were shown to permit, inter alia, a reduction of 25 percent in PLA area. But surface area of integrated circuit chips is continually at a high premium. Consequently, a constant problem for the integrated circuit designer is implementing increasing numbers of functions with less and less chip surface area.